1. Field of the Invention
The present invention relates to method and apparatus for synchronization when signals in accordance with IEEE (Institute of Electrical and Electronics Engineers) 1394 are transmitted over a medium of half duplex transmission.
2. Description of the Background Art
Standards and draft standards such as high performance serial bus IEEE Std 1394-1995 (and P1394a and P1394b proposed as additional specification thereof) have been known as prior art techniques of this field. In such (draft) standards, nodes connected to a bus are synchronized by providing a packet for synchronization, which is called a cycle start packet, over the bus once at every 125 micro seconds.
The cycle start packets are transmitted by a node called a cycle master node, which has a cycle timer register serving as a reference for synchronization.
FIG. 1 represents a format of the cycle start packet. Referring to FIG. 1, a cycle start packet consists of a total of 160 bits. FIG. 1 represents the 160 bits in the form of 32 bitsxc3x975 stages. The cycle start packet includes, in the order of transmission, the first field of 16 bits representing a packet destination nodes; the second field of 8 bits; the third field of 4 bits representing the type of the packet; the fourth field of 4 bits representing packet priority; the fifth field of 16 bits representing a transmission node; the sixth field of 48 bits representing a destination address; the seventh field of 32 bits representing a value of the cycle time register at the cycle master node at the time of packet transmission; and the eighth field of 32 bits storing a CRC (Cyclic Redundancy Check) code for validating whether the contents of the packet are correct.
The value of the first field is xe2x80x9cFFFFxe2x80x9d in hexadecimal notation, representing that the packet is a broadcast packet. The xe2x80x9cbroadcast packetxe2x80x9d refers to a packet which is addressed to all the nodes connected to the bus.
The value stored in the second field is, for the cycle start packet, always xe2x80x9c00xe2x80x9d in hexadecimal notation.
The third field stores the value of xe2x80x9c8xe2x80x9d in hexadecimal notation (xe2x80x9c1000xe2x80x9d in binary notation) for the cycle start packet.
The value stored in the fourth field is, for the cycle start packet, always the value representing the highest priority (xe2x80x9cFFFFxe2x80x9d in hexadecimal notation).
The fifth field stores a value representing a transmission node of the cycle start packet.
The sixth field stores, for the cycle start packet, an address of the cycle timer register holding time information at each node (xe2x80x9cFFFFF0000200xe2x80x9d in hexadecimal notation).
The contents related to the value of the cycle time register stored in the seventh field will be described later.
FIG. 2 represents the configuration of the cycle time register described above. The cycle time register is a 32-bit register, which is used divided into xe2x80x9csecond_countxe2x80x9d of 7 bits, xe2x80x9ccycle_countxe2x80x9d of 13 bits and xe2x80x9ccycle_offsetxe2x80x9d of 12 bits.
xe2x80x9cSecond_countxe2x80x9d is a field representing seconds, which is incremented by a carry of xe2x80x9ccycle_countxe2x80x9d, which will be described later.
xe2x80x9cCycle_countxe2x80x9d is a field representing a number of cycles each equal to one 8000th of a second. This field is incremented by a carry of xe2x80x9ccycle_offsetxe2x80x9d, which will be described later, and when the value of this field reaches 8000, it is carried up and reset to 0. When this field is reset, the value of xe2x80x9csecond_countxe2x80x9d field is incremented.
xe2x80x9cCycle_offsetxe2x80x9d is a field representing an offset in a cycle counted at a clock of 24.576 MHz. This field is incremented by the clock of 24.576 MHz and when the value reaches 3072, it is carried up and reset to 0. When this field is reset, xe2x80x9ccycle_countxe2x80x9d field is incremented. The offset in the third field is delay information from the reference start time of the cycle.
Each node repeats all the packets including the received cycle start packet to ports other than a reception port, with an almost constant repeat delay time. Thus, the packets are transmitted to all the nodes. Each node updates contents of a cycle time register of the node itself, by the time information contained in the received cycle start packet. This enables synchronization of the entire bus. This will be described with reference to FIGS. 3 and 4.
In the following description, three nodes 100a (node A), 100b (node B) and 100c (node C) are daisy-chain-connected using an IEEE 1394 bus 101, as shown in FIG. 3. Internal configurations of the nodes are identical. Therefore, these nodes may sometimes be generally referred to a node 100.
In the example shown in FIG. 3, it is assumed that node A is the cycle master node.
Referring to FIG. 4, each node 100 has a physical layer controller 110 and a link layer controller 120. A node which performs a repeat process only, which will be described later, may have the physical layer controller only.
Physical layer controller 110 has at least one port 111 for exchanging data over bus 101. Physical layer controller 110 includes a reception data bus 12 for propagating data received at port 111, a transmission data bus 13 for propagating data to be transmitted from port 111, a resynchronization unit 14 for synchronizing received data with a local clock, and a link layer I/F15 which is an interface with link layer controller 120.
Link layer controller 120 includes a cycle time register 121, and a physical layer I/F 122 which is an interface with physical layer controller 110.
In a state where the cycle start packet is to be transmitted, node A (100a) as the cycle master node issues a transmission request to IEEE 1394 bus. When transmission is enabled, the cycle start packet including the contents of cycle time register 121 of node A (100a) as the cycle master node is formed by link layer controller 120, and transmitted through physical layer I/F 122 in link layer controller 120, link layer 1/F15 in physical layer controller 110, transmission data bus 13 and port 111. Nothing is transmitted from port 111 which is not connected to anywhere.
Node B (100b) connected to cycle master node (node A) by the IEEE 1394 bus applies the packet data received from port 111 through reception data bus 12 to resynchronization unit 14. The received packet data is re-synchronized with the local clock of node B at resynchronization unit 14, and transmitted through the transmission data bus 13 from port 111 other than the port which has received the data. This is the process referred to as xe2x80x9crepeat.xe2x80x9d
In parallel with the repeat process, node B (100b) transmits the re-synchronized packet data to link layer controller 120 through link layer I/F15 and physical layer I/F122. When the packet is the cycle start packet, a value of cycle time register 121 in link layer controller 120 is updated by the value of xe2x80x9ccycle_timexe2x80x9d field contained therein.
Node C (100c) connected to node B (100b) by the IEEE 1394 bus rewrites the value of cycle time register 121 in link layer controller 120, by the value of the xe2x80x9ccycle_timexe2x80x9d field contained in the cycle start packet which has been re-synchronized with the local clock at node C (100c), similar to node B (100b). In the example of FIG. 3, there is not the port 111 which is connected to anywhere other than the port 111 which has received the data at node C, and therefore, repeat process does not take place.
By the above described operation, the three nodes (100a, 100b and 100c) can be synchronized.
Though there are three nodes in the example of FIG. 3, larger number of nodes may be connected. Such an example may be considered as having a plurality of nodes corresponding to node B (100b) connected in a longer daisy chain. Alternatively, or in addition, nodes corresponding to node A or node B may have a plurality of transmission destination (repeat destination) ports and in star connection.
Another prior art example includes an IEEE 1394 bridge connecting two IEEE 1394 buses, which is discussed for standardization by P1394.1, one of Standards Committees of IEEE. In IEEE 1394 bridge, a scheme has been considered in which a cycle start packet of one bus is generated based on time information contained in the cycle start packet of the other bus, so as to attain synchronization between the two buses connected thereto.
FIG. 5 shows an example of the IEEE 1394 bridge. Referring to FIG. 5, a bridge 200 as an example of IEEE 1394 bridge includes physical layer controllers 110, 110xe2x80x2 and link layer controllers 120, 120xe2x80x2 provided corresponding to bus 201 (bus A) and bus 201xe2x80x2 (bus B) as IEEE 1394 buses connected thereto, respectively, as well as a bridge controller 210 connected to the two link layer controllers 120 and 120xe2x80x2.
The two physical layer controllers 110 and 110xe2x80x2 receives, among the packet data flowing over connected buses 201 and 201xe2x80x2 respectively, those addressed to themselves or nodes addressed to all the nodes connected to buses 201 and 201xe2x80x2, and pass the received packet data to link layer controllers 110 and 110xe2x80x2 connected thereto. Further, physical layer controllers 110 and 110xe2x80x2 transmit packet data of which transmission is indicated by link layer controllers 120, 120xe2x80x2, to buses 201 and 201xe2x80x2, respectively.
Two link layer controllers 120 and 120xe2x80x2 transmit the received data from the buses received through physical layer controllers 110 and 110xe2x80x2 connected thereto, respectively, to bridge controller 210. Link layer controllers 120 and 120xe2x80x2 instructs physical layer controllers 110 and 110xe2x80x2 to transmit the data transmitted from bridge controller 210 to the buses. Link layer controller 120 or 120xe2x80x2 which is connected to a bus where the bridge 200 is the cycle master node generates the cycle start packet, and indicates transmission of the cycle start packet to the connected physical layer controller 110 or 110xe2x80x2.
Bridge controller 210 determines whether the repeat to the other bus should be performed or not, in accordance with bus information of the destination of the receive packet. When repeating is to be done, bridge controller 210 issues a command to transmit the packet to be repeated, to the link layer controller. The cycle start packet is not repeated by the bridge controller.
Different from the first prior art example, in bridge 200, the cycle time register holding time information of the bus is not provided in each of the two link layer controllers 120 and 120xe2x80x2 but one common cycle time register is used.
Here, it is assumed that the cycle start packet is received from the side of bus A(201), and the cycle start packet is generated and output to the side of bus B(201)xe2x80x2. Naturally, on the side of bus B, bridge 200 serves as the cycle master node.
Link layer controller 120 connected to bus A updates the cycle time register in accordance with the contents of the cycle start packet.
Link layer controller 120xe2x80x2 connected to bus B generates the cycle start packet by reading the contents of the cycle time register, and transmits the generated packet to bus B.
It is possible that a cycle start packet is not received but the cycle start packet is transmitted to both buses. It occurs when buses A and B are performing the same process. In this case, bridge 200 is referred to as a bus cycle master node.
When it is unnecessary for bus A or bus B or both connected to bridge 200 to handle a synchronization packet referred to as an isochronous packet, the bridge may not receive or transmit the cycle start packet.
However, half duplex transmission (ping-pong transmission) is not possible in accordance with IEEE Std 1394-1995, P1394a and P1394b .
Transmission of signals in accordance with IEEE 1394 using half duplex transmission (ping-pong transmission) may be considered. In that case, however, repeat delay at each node is not constant. Therefore, simple repeating may cause mismatch of time information among nodes on the bus. This problem will be described with reference to FIGS. 6 to 8.
FIG. 6 represents packet timings in the link layer controller on the cycle start packet transmitting side (cycle master node).
Referring to FIG. 6, delay time x from a reference of a cycle when the cycle start packet is transmitted (that is, the time point at which cycle offset of cycle timer of the cycle master node is 0) is transmitted, contained in the cycle start packet.
FIG. 7 represents packet timings in the link layer controller on the cycle start packet receiving side, when IEEE 1394 is used as the transmission medium.
Referring to FIG. 7, delay time xcex4 0 at the time of transmission and reception is almost constant. Therefore, updating of local time information using the time information contained in the received cycle start packet causes no mismatch.
FIG. 8 represents packet timings in the link layer controller on the cycle start packet receiving side, when a half duplex transmission medium is used as the transmission medium. In the figure, the delay time xcex4 0 represents the total delay time at transmission and reception, at the nodes between the transmitting and receiving sides (including the transmitting node and the receiving node themselves).
Here, though the delay time is almost constant at the time of reception, the delay time is not constant for transmission. Therefore, when the local time information is updated using the time information contained in the received cycle start packet, time mismatch results. The delay times xcex4 1 and xcex4 2 represent the total of delay times for transmission and reception, similar to delay time xcex4 0. More specifically, because of the variation in the transmission delay time, the time may considerably be advanced or lagged behind, when the local time is updated on the receiving side. The variation in the transmission delay time experienced here is a few microseconds.
As the time is considerably advanced or lagged behind, synchronization between nodes may possibly be unsatisfactory, and isochronous (synchronized) data handling, which is on the premise that the nodes are in synchronization, may be difficult.
When a bridge is used, the cycle start packet is not repeated but a new cycle start packet is generated. Therefore, there is not the problem of mismatch in time information between buses. The bridge configuration, however, is complicated as shown in FIG. 5, and implementation of the bridge increases the circuit scale. Further, as there are two or more divided buses involved, a mechanism for passing packets to and from nodes on different buses over the bridge becomes necessary.
Therefore, an object of the present invention is to provide a method of half duplex transmission transmitting packetized digital data which can be realized in a simple and small scale circuit without causing time information mismatch among buses.
Another object of the present invention is to provide a method of half duplex transmission transmitting packetized digital data implemented by a simple and small scale circuit using a small amount of information without causing time information mismatch among buses.
A still further object of the present invention is to provide a method of half duplex transmission transmitting packetized digital data implemented by a simple and small scale circuit without causing time information mismatch on a serial bus.
An additional object of the present invention is to provide a method of half duplex transmission transmitting packetized digital data implemented by a simple and small scale circuit with a small amount of information, without causing time information mismatch.
The present invention provides a method of half duplex transmission of packetized digital data from an electronic device to another node through a bus connected to the electronic device. The electronic device has at least one transmitting/receiving unit for transmitting and receiving a packet on the bus. The method includes the steps of: inputting a new packet to be transmitted to a first-in-first-out storage; determining whether the new packet input to the first-in-first-out storage contains time information related to synchronization with another electronic device; updating a local timer of the electronic device with a prescribed value in response to determination that the new packet contains time information; continuously incrementing the local timer; in response to a timing enabling transmission of the new packet by the transmitting/receiving unit, reading the new packet from the first-in-first-out storage, determining whether the new packet contains time information or not, updating the time information contained in the new packet by using a local timer value so as to prevent mismatch of synchronization with another electronic device, and outputting the new packet to the bus through the transmitting/receiving unit.
When the new packet containing the time information is to be transmitted, the local timer is updated using the time information of the packet, and the local timer is continuously incremented. At the time of actual output, the time information contained in the packet to be transmitted is rewritten by using the value of the local timer, and therefore time synchronization mismatch with the other electronic device can be prevented even in the half duplex transmission. Further, the circuit used therefor may be a simple, small scale circuit.
Preferably, information length of the local timer is equal to the information length of the time information, and the step of updating includes the step of rewriting the local timer with the time information of the new packet in response to the determination that the new packet contains time information.
More preferably, the information length of the local timer is shorter than the length of the time information, and the step of updating the step of rewriting the local timer with lower information of the time information of the new packet, in response to the determination that the new packet contains time information.
More preferably, the step of updating includes the step of rewriting the local timer value to a predetermined constant, for example, 0, in response to the determination that the new packet contains time information. The step of outputting includes the step of reading, in response to the timing enabling transmission of the new packet by the transmitting/receiving unit, the new packet from the first-in-first-out storage, determining whether the new packet contains time information or not, adding an addition value of the local timer rewritten by the step of rewriting to the time information contained in the new packet so as to rewrite the time information contained in the new packet, and outputting the packet to the bus through the transmitting/receiving unit.
According to another aspect, the present invention provides a half duplex transmission apparatus for half duplex transmission of packetized digital data from an electronic device to another node through bus connected to the electronic device, and the electronic device has at least one transmitting/receiving unit for transmitting/receiving the packet on the bus. The apparatus includes: a first-in-first-out storage connected to receive the new packet to be transmitted; a local timer updated with a prescribed value when the new packet input to the first-in-first-out storage contains time information related to synchronization with another electronic device and counted up with a prescribed clock signal; and a packet rewriting unit responsive to the timing enabling transmission of the new packet by the transmitting/receiving unit, reading the new packet from the first-in-first-out storage, determining whether the new packet contains time information or not, changing the time information contained in the new packet by using the local timer value, and outputting the packet to the bus through the transmitting/receiving unit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.